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A 1.2V high conversion gain mixer with reused gm stage in 65nm CMOS

Jianhui Wu, Chao Chen, Xincun Ji
2013 IEICE Electronics Express  
A 1.2 V high conversion gain mixer which reuses the gm stage of the mixer as RF and IF amplifying stage is proposed in this paper.  ...  A high conversion gain of 30 dB is achieved with the power consumption of 3 mW under a 1.2 V supply voltage.  ...  Conclusions This paper proposes a high conversion gain mixer with reused RF and IF gm (transconductance) stage.  ... 
doi:10.1587/elex.10.20130279 fatcat:iya6c7qy6vdododngeawzvudva

RFIC 2020 Program

2020 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  
The receiver achieves an in-band IIP3 of +14dBm, a gain of 15dB and a noise figure of 12.5dB. RTu1B-3 A 9-31GHz 65nm CMOS Down-Converter with >4dBm OOB B1dB Zachariah G.  ...  The 2-stage PA achieves a peak gain of 21.4dB with a fractional BW of 22.6% (51-64GHz).  ...  A modulator that provides outphasing signals to synthesize RF-PWM without a narrow pulse-width limitation is proposed. The Cartesian transmitter is implemented in a 65-nm CMOS process.  ... 
doi:10.1109/rfic49505.2020.9218389 fatcat:fqkpw3oau5gzpoi3gscgb7kwhi

Design of PVT tolerant inverter based circuits for low supply voltages

Ramesh Harjani, Rakesh Kumar Palani
2015 2015 IEEE Custom Integrated Circuits Conference (CICC)  
in gain stage.  ...  The prototype designed in TSMC's 65nm general purpose CMOS for 236mV nominal voltage, shows a temperature coefficient of 18 ppm/ • C from −40 to 100 • C with a power supply ranging from 0.8 to 2V  ... 
doi:10.1109/cicc.2015.7338424 dblp:conf/cicc/HarjaniP15 fatcat:7xagokignreatbvmontp3vnihm

Bandpass Delta-Sigma Converters in IF Receivers [chapter]

Armond Hairapetian
2001 Analog Circuit Design  
This symbolizes the convergence of single application phones, that only can be used to connect to a single type of network, into more agile, multi-standard phones with an increasing amount of functionality  ...  The battery symbolizes the limited amount of energy available in mobile devices and therefore the high efficiency required from all its building blocks.  ...  The active circuitry is implemented solely with inverter circuits and standard digital cells in a 65nm CMOS technology. Power consumption is 950µW at 1.2V and the area is only 0.03mm 2 .  ... 
doi:10.1007/978-1-4613-1443-1_10 fatcat:cg34vk7z65cgleckvjw5lbhiqe

Configurable circuits and their impact on multi-standard RF front-end architectures [article]

Vidojkovic, M (Maja), Baltus, PGM (Peter), Roermund, AHM (Arthur) Van, Tang, JD (Johan) Van Der
2011
The front-end implemented in 65nm CMOS outperforms the front-end implemented in 90nm CMOS.  ...  Two wide-band RF front-end circuits have been implemented in 90nm CMOS and 65nm CMOS, while one combined multi-standard RF front-end circuit has been designed in 65nm CMOS.  ...  In case the voltage gain is high, the linearity can be improved by increasing the output resistance of the MOS transistor.  ... 
doi:10.6100/ir695312 fatcat:zsky42gawzffnfssqncn4vpaa4

Parallel-sampling ADC architecture for power-efficient broadband multi-carrier systems [article]

Y Yu Lin, AHM Arthur Van Roermund, JA Hans Hegt
2014
This stage is designed and simulated using CMOS 65nm technology with only thin-oxide transistors and a single 1.2V supply voltage.  ...  The schematics of this stage are shown in Figure 4.1.4. Circuits of this stage were implemented using 65nm CMOS technology. The stage operates at 200MS/s and with a 1.2V supply.  ...  Acknowledgement When I was a teenager, I enjoyed climbing mountains and exploring "hidden lands". My feeling of pursuing a PhD has a lot in common with a mountain journey.  ... 
doi:10.6100/ir782336 fatcat:mxnwyvimszgc5pvz4quvrx2fvm

Direct sampling receivers for broadband communications

Fang, Jie, (Ph. D.), 0000-0002-3568-5180, Austin, The University Of Texas At, Austin, The University Of Texas At, Jacob A. Abraham
2019
Three prototypes: the broadband RF front ends with RFPGA-V, the broadband RF front ends with RFPGA-I and a 5-GHz ADC, are fabricated to verify the proposed ideas in 28nm CMOS technology.  ...  RFPGA-V and RFPGA-I utilize an innovative interpolation method and current steering approach, respectively, to achieve a fine gain step of 0.25-dB over 40-dB gain range for several GHz frequency range.  ...  Comparing with the analog channel selection using analog mixer and IF filters in a superheterodyne receiver, the digital channel selection is realized by using digital mixers and filters in a DS receiver  ... 
doi:10.26153/tsw/2178 fatcat:kvn5fzh37nf33cp5acelhrqvzy

Flexible phase-locked loops and millimeter wave PLL components for 60-GHz wireless networks in CMOS [article]

Cheema, HM (Hammad), Roermund, AHM (Arthur) Van, Mahmoudi, R (Reza)
2010
The work leading to this thesis has been performed in the framework of WiComm: Microelectronics for the next generation of wireless communication project which is a part of a Dutch national research program  ...  Synthesizer with down-conversion mixer in feedback loop The replacement of the divider chain in the feedback loop with a mixer was proposed in section 5.1.2.  ...  First, is the cascade of divideby-2 stages and second is the down-conversion utilizing a mixer.  ... 
doi:10.6100/ir657030 fatcat:tolw5no2rbavzf3uj6zlw4uh3y

High-accuracy switched-capacitor techniques applied to filter and ADC design [article]

Quinn, PJ (Patrick), Roermund, AHM (Arthur) Van
2006
The ADC is embedded in 65nm CMOS in a complex SoC and proven to be very robust.  ...  The SC techniques presented here are fully compatible with CMOS technology and have been proven on CMOS down to 65nm. The amplifier is the most important component in a SC circuit.  ...  There he is team leader and technical lead of advanced mixed-signal IC design projects for Virtex FPGAs down to 65nm CMOS.  ... 
doi:10.6100/ir611679 fatcat:v2gw45jsvfelbpyhsrxe5fxxmq