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2021 IEEE International Solid- State Circuits Conference (ISSCC)
A 3D NAND flash memory continues to increase in bit density and performance for both local and cloud data storage applications. ... A floorplanning technique used to put page buffer circuits into a small area under a highly-stacked memory array is shown in paper 30.1. ... Low-tapped termination-type circuits that support a 2.0Gbps interface are introduced. 8:54 AM A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology Tsutomu Higuchi, KIOXIA, Yokohama, Japan ...doi:10.1109/isscc42613.2021.9365847 fatcat:5qsiqkiiezagniqgq6r2sgoojm