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3-D floorplanning: simulated annealing and greedy placement methods for reconfigurable computing systems

K. Bazargan, R. Kastner, M. Sarrafzadeh
Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246)  
In this paper we present offline placement algorithms based on simulated annealing and greedy methods and show the superiority of their placements over the ones generated by an online algorithm.  ...  In the case of offline placement, we are willing to spend more time during compile time to find a compact floorplan for the RFU modules and utilize the RFU area more efficiently.  ...  We devised simulated annealing and greedy placement methods for the 3-D placement of the RFUOPs and showed their effectiveness.  ... 
doi:10.1109/iwrsp.1999.779029 dblp:conf/rsp/BazarganKS99 fatcat:o4zeyfayezgpdcarkjhlny7cgq

Temporal floorplanning using the three-dimensional transitive closure subGraph

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007 ACM Transactions on Design Automation of Electronic Systems  
In this paper, we use a novel graph-based topological floorplan representation, named 3D-subTCG (3-Dimensional Transitive Closure subGraph), to deal with the 3-dimensional (temporal) floorplanning/placement  ...  We also derive important properties of the 3D-subTCG to reduce the solution space and shorten the running time for 3D (temporal) foorplanning/placement.  ...  Experimental results have shown that our method is very effective and efficient for temporal floorplanning/placement.  ... 
doi:10.1145/1278349.1278350 fatcat:bqinfcyl3bcqbpqikgf25nx3hu

Efficient FPGA Floorplanning for Partial Reconfiguration-Based Applications [article]

Norbert Deak, Octavian Creţ, Horia Hedeşiu
2019 arXiv   pre-print
Most of them are defined for old FPGA architectures and have a high computational time.  ...  The algorithm generates possible placements of the partial modules, then applies a recursive pseudo-bipartitioning heuristic search to find the best floorplan.  ...  In [9] slicing trees are used to represent an FPGA floorplan and simulated annealing, one of the most common algorithms in FP [7] , to find the optimal result.  ... 
arXiv:1904.10646v1 fatcat:vgtzk5yzsjhallwovtsu4w2rqi

A methodology for fast FPGA floorplanning

John M. Emmert, Dinesh Bhatia
1999 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays - FPGA '99  
In this paper we present a macro based floorplanning methodology suitable for mapping large circuits to large, high density FPGAs.  ...  Our method is capable of handling both hard (fixed size and shape) macros and soft (fixed size and variable shape) macros.  ...  Many recent papers have addressed placement and floorplanning for regular arrays. Rose et. al. use simulated annealing as the basis of their placement tool[2].  ... 
doi:10.1145/296399.296427 dblp:conf/fpga/EmmertB99 fatcat:huk7njxmofcnhi2sliid7ctvzy

A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment

Yih-Lang Li, Yu-Ning Chang, Wen-Nai Cheng
2011 ACM Transactions on Design Automation of Electronic Systems  
For detailed routing, this work proposes a rapid extraction method for pseudomaximum stripped tiles to boost path propagation.  ...  Experimental results demonstrate that the proposed gridless routing system has over 2.02 times the runtime speedup in average for fixed-and variablerule routings of an implicit connection-graph-based router  ...  For GTA, the simulated annealing process is not desired, since many panels are involved in decreasing crosstalk, and the total runtime is unacceptable.  ... 
doi:10.1145/1929943.1929951 fatcat:vwhseophcbdbllpdk5dsotvjla

Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
2007 ACM Journal on Emerging Technologies in Computing Systems  
Experimental results demonstrate that our approach is more efficient and effective than the previous unified synthesis and placement framework.  ...  As biochips are adopted for the complex procedures in molecular biology, its complexity is expected to increase due to the need of multiple and concurrent assays on a chip.  ...  THE FLOORPLANNING ALGORITHM Our algorithm is based on the simulated annealing (SA) method [Kirkpatrick et al. 1983 ].  ... 
doi:10.1145/1295231.1295234 fatcat:icuidp3mpnfalpk5pbbkcg7txa

Design space exploration for partially reconfigurable architectures in real-time systems

François Duhem, Fabrice Muller, Willy Aubry, Bertrand Le Gal, Daniel Négru, Philippe Lorenzini
2013 Journal of systems architecture  
The flow is based upon our SystemC simulator for real-time systems that helps develop and validate scheduling algorithms with respect to application timing constraints and partial reconfiguration physical  ...  In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints,  ...  dynamic and partial reconfiguration.  ... 
doi:10.1016/j.sysarc.2013.06.007 fatcat:dixe4ecqyrce7prltrqkvrxaze

New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA

Ikbel Belaid, Fabrice Muller, Maher Benjemaa
2010 International Journal of Reconfigurable Computing  
Hence, the placement problem is formulated into a constrained optimization problem and resolved with powerful solvers using the Branch and Bound method.  ...  Improving placement quality will produce significant enhancement of performance for scheduling and overall execution time of the application in FPGA.  ...  Acknowledgments This paper was supported by AIMMS technical support and Xilinx tools.  ... 
doi:10.1155/2010/980762 fatcat:kninukuahrc57ponkh3g6raloi

Transformation from ad hoc EDA to algorithmic EDA

Jason Cong
2012 Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design - ISPD '12  
floorplanning, placement, routing, FPGA synthesis, high-level synthesis, and fault-tolerant designs.  ...  Finally, I discuss his contributions as a great educator-one who has trained multiple generations of leaders, researchers and entrepreneurs in EDA and beyond.  ...  I would also like to thank Liu's former students, Taewhan Kim, Ran Libeskind-Hadas, Anmal Mather, and Peichen Pan, for providing highlights of their research work with Dave.  ... 
doi:10.1145/2160916.2160929 dblp:conf/ispd/Cong12 fatcat:kbukjfejkjhirlqcy772ikeppy

Temporal floorplanning using 3D-subTCG

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)  
In this paper, we use a novel topological floorplan representation, named 3D-subTCG (3-Dimensional sub-Transitive Closure Graph) to deal with the 3dimensional (temporal) floorplanning/placement problem  ...  We also derive important properties of the 3D-subTCG to reduce the solution space and shorten the running time for 3D (temporal) foorplanning/placement.  ...  Acknowledgements This work is supported in part by the National Science Council under Grand NSC 92-2213-E-002-014-and NSC 92-215-E-002-043-. We would also thank to anonymous reviewers.  ... 
doi:10.1109/aspdac.2004.1337688 fatcat:upquynbewbelzfb2gpezbibkim

Temporal floorplanning using the T-tree formulation

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.  
In this paper, we model each task as a 3D-box and deal with the temporal floorplanning/placement problem for dynamically reconfigurable FPGA architectures.  ...  For the T-tree, we develop an efficient packing method and derive the condition to ensure the satisfaction of precedence constraints which model the temporal ordering among tasks induced by the execution  ...  Temporal Floorplanning Algorithm Our floorplanning algorithm is based on the simulated annealing method [13] .  ... 
doi:10.1109/iccad.2004.1382590 dblp:conf/iccad/YuhYC04 fatcat:2o5bmnxvbvettkuusf6vdu6dim

Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology [chapter]

D. J. Hathaway, R. R. Habra, E. C. Schanzenbach, S. J. Rothman
1997 High Performance Clock Distribution Networks  
Circuit placement is done using algorithms which have been used within IBM for many years, with enhancements as required to support additional technologies and larger data volumes.  ...  There are numerous user controls for specifying router behavior in particular areas and on particular interconnection levels, as well as adjacency restrictions.  ...  For example, the simulated annealing placement program now has the capability of performing low-temperature simulated annealing (LTSA).  ... 
doi:10.1007/978-1-4684-8440-3_7 fatcat:jlowhkvglnd7nbw7csxpggyolm

Circuit placement, chip optimization, and wire routing for IBM IC technology

D. J. Hathaway, R. R. Habra, E. C. Schanzenbach, S. J. Rothman
1996 IBM Journal of Research and Development  
Circuit placement is done using algorithms which have been used within IBM for many years, with enhancements as required to support additional technologies and larger data volumes.  ...  There are numerous user controls for specifying router behavior in particular areas and on particular interconnection levels, as well as adjacency restrictions.  ...  For example, the simulated annealing placement program now has the capability of performing low-temperature simulated annealing (LTSA).  ... 
doi:10.1147/rd.404.0453 fatcat:wjrdl5bmo5f37cnumjcoaq7pim

FoRTReSS: a flow for design space exploration of partially reconfigurable systems

François Duhem, Fabrice Muller, Robin Bonamy, Sébastien Bilavarn
2015 Design automation for embedded systems  
home gateways integrating dynamic and partial reconfiguration.  ...  This work is also carried out under the BENEFIC project (CA505), a project labelled within the framework of CATRENE, the EUREKA cluster for Application and Technology Research in Europe on NanoElectronics  ...  Processor selection for simulation While FoRTReSS focus is on the determination and placement of reconfigurable regions, it is also possible to design mixed systems including one or more software processing  ... 
doi:10.1007/s10617-015-9160-2 fatcat:w6bcrsardbbi3ocnqleoxpprvi

Integrated logic synthesis using simulated annealing

Petra Färm, Elena Dubrova, Andreas Kuehlmann
2011 Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '11  
We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution.  ...  The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and  ...  A greedy local transformation-based method. 2. Simulated annealing at And/Inverter graph level. 3 . A combined technology independent and technology dependent optimization technique. 4 .  ... 
doi:10.1145/1973009.1973095 dblp:conf/glvlsi/FarmDK11 fatcat:dlju72re25ae7jgninv5kuntia
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