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The Paramountcy of Reconfigurable Computing [chapter]

Reiner Hartenstein
2012 Energy-Efficient Distributed Computing Systems  
This chapter shows that Reconfigurable Computing is the silver bullet to obtain massively better energy efficiency as well as much better performance, also by the upcoming methodology of HPRC (high performance  ...  high performance computing.  ...  FPGAs from a new Xilinx 28nm high-performance, low-power process, developed by Xilinx and TSMCoptimized for high performance & low power are much better off than GPUs (Table 7) 187 .  ... 
doi:10.1002/9781118342015.ch18 fatcat:shfb4oycu5hu5boizx6oltlgwa

Understanding and Improving the Latency of DRAM-Based Memory Systems [article]

Kevin K. Chang
2017 arXiv   pre-print
Our new techniques significantly improve both system performance and energy efficiency.  ...  other new mechanisms to improve the performance, energy efficiency, or reliability of future memory systems.  ...  In summary, LISA-RISC provides both high performance and high memory energy efficiency for bulk data copying for a wide variety of single-and multi-core workloads.  ... 
arXiv:1712.08304v1 fatcat:6y2nr2eowvb5fhr7km7azmkioe

Rapid SoC Design: On Architectures, Methodologies and Frameworks [article]

Adetutu Ajayi, University, My
2021
This holds true across the spectrum, from mobile/handheld processors to high-performance data-center appliances.  ...  For several decades, chip designers have relied on Moore's Law - the doubling of transistor count every two years to deliver improved performance, higher energy efficiency, and an increase in transistor  ...  arrays of small, tightly coupled cores that attain high energy efficiency and flexibility for evolving workloads.  ... 
doi:10.7302/1546 fatcat:hekqywqyznaihaisver5be4t4y

INGEGNERIA ELETTRONICA, TELECOMUNICAZIONI E TECNOLOGIE DELL'INFORMAZIONE Ciclo XXVIII Memory Hierarchy Design for Next Generation Scalable Many-core Platforms Coordinatore Dottorato Relatore Memory Hierarchy Design for Next Generation Scalable Many-core Platforms

Vanelli Alessandro, Coralli, Luca Benini, Erfan Azarkhish
2016 unpublished
These two directions bring about several interesting opportunities including performance improvement, energy and cost reduction, product miniaturization, and modular design for improved time to market.  ...  Igor Loi and Dr. Davide Rossi for helping me during this research and for their valuable and insightful comments.  ...  Also, because most application processors and almost all mobile SoCs feature a large on-chip L2 memory which is shared by multiple cores.  ... 
fatcat:e2rk56rc4naoljdxduijinhqgy

Understanding and Improving the Latency of DRAM-Based Memory Systems

Kevin K. Chang
2018
The use of this narrow channel for bulk data movement results in high latency and high energy consumption.  ...  Our new techniques significantly improve both system performance and energy efficiency.  ...  In summary, LISA-RISC provides both high performance and high memory energy efficiency for bulk data copying for a wide variety of single-and multi-core workloads. .14 shows the system performance improvement  ... 
doi:10.1184/r1/6724127.v1 fatcat:gjvlf6dju5eg3kjz6nfjn3shie