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Session 22 Overview: DRAM & High-Speed Interfaces: Memory Subcommittee

2020 2020 IEEE International Solid- State Circuits Conference - (ISSCC)  
GDDR6 PHY with the compensation of ISI and FEXT is presented, and a quadrature-error-corrector with error range of 106ps for a DRAM interface is also presented.  ...  Two HBM DRAM papers of next generation show maximum data rates of 512~640GB/s, and 12Gb LPDDR5 with 8.5Gb/s/pin in a 2 nd generation 10nm process node are introduced.  ...  It achieves 32Gb/s/pin with the energy efficiency of 0.97pJ/b due to a digital-intensive time domain comparison. 11:45 AM 22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training  ... 
doi:10.1109/isscc19947.2020.9063160 fatcat:3s7yj3fe3berfpx3paapgnp5uy