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11b 60 MHz pipelined ADC with inverter-based class AB amplifier in 28 nm CMOS technology

Zihui Wei, Yanbin Xiao, Shuilong Huang
2017 IEICE Electronics Express  
An inverter-based class AB amplifier is proposed to design the 11b pipelined analogue-to-digital converter (ADC) in 28 nm CMOS technology.  ...  The structure of the proposed amplifier is more concise compared with conventional amplifiers. The amplifier occupies small area, and its quiescent dissipation is only 1.4 mA.  ...  Acknowledgments This work was supported by the National Science and Technology Major Project 02 of China (no. 2014ZX02302002).  ... 
doi:10.1587/elex.14.20170047 fatcat:ussfxxklxrha3elxt64kjqu5au

A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System

Dongdong Chen, Xinhui Cui, Qidong Zhang, Di Li, Wenyang Cheng, Chunlong Fei, Yintang Yang
2022 Micromachines  
In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced  ...  In addition, comparisons and discussions of different types of ADCs are presented.  ...  [59] proposed a split-pipelined ADC with a closed-loop class AB residual amplifier (as shown in Figure 14b ).  ... 
doi:10.3390/mi13010114 pmid:35056279 pmcid:PMC8779678 fatcat:nxirhfhgzjcvlojql2k6sflxfi

A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

Juyong Lee, Seungjun Lee, Kihyun Kim, Hyungil Chae
2021 Electronics  
The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.  ...  The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed.  ...  Reference VLSI'14 [10] CICC'14 [11] EDSSC'19 [12] ISCAS'17 [13] Technology 28 nm CMOS 65 nm CMOS 65 nm CMOS 40 nm CMOS ADC Type Pipeline-SAR Pipeline-SAR Pipeline-SAR Pipelined Signal to  ... 
doi:10.3390/electronics10161968 fatcat:2mu2hpql65fflej45kpgyqvp3m

Parallel-sampling ADC architecture for power-efficient broadband multi-carrier systems [article]

Y Yu Lin, AHM Arthur Van Roermund, JA Hans Hegt
architectures such as class-AB amplifiers, comparator based amplifiers, dynamic amplifiers, and so on.  ...  for a 4GS/s 11b time-interleaved ADC using 40nm CMOS technology were presented in chapter 4.  ...  My feeling of pursuing a PhD has a lot in common with a mountain journey.  ... 
doi:10.6100/ir782336 fatcat:mxnwyvimszgc5pvz4quvrx2fvm

Direct sampling receivers for broadband communications

Fang, Jie, (Ph. D.), 0000-0002-3568-5180, Austin, The University Of Texas At, Austin, The University Of Texas At, Jacob A. Abraham
Three prototypes: the broadband RF front ends with RFPGA-V, the broadband RF front ends with RFPGA-I and a 5-GHz ADC, are fabricated to verify the proposed ideas in 28nm CMOS technology.  ...  Today everything tends to be connected in the Internet of Things (IoT) universe, where a broad variety of communication standards and technologies are used for those connected devices.  ...  is an inverter-based class-AB CS amplifier, which provides the most of gain in the amplifier.  ... 
doi:10.26153/tsw/2178 fatcat:kvn5fzh37nf33cp5acelhrqvzy

Physics and Detectors at CLIC: CLIC Conceptual Design Report [article]

Lucie Linssen, Marcel Stanitzki
2012 arXiv   pre-print
This report describes the physics potential and experiments at a future multi-TeV e+e- collider based on the Compact Linear Collider (CLIC) technology.  ...  After optimisation of the detector concepts and adopting the reconstruction algorithms the results show very efficient background rejection and clearly demonstrate the physics potential at CLIC in terms  ...  Acknowledgements The CLIC physics and detector, described in this document, benefited from the ILC detector R&D efforts, which were supported by BMWF, Austria;  ... 
arXiv:1202.5940v1 fatcat:36rj7sfqafgfxcgxq4l3wt5jdm

A New Approach to Learning in Neuromorphic Hardware

Simon Friedmann
Der Prozessor wurde auch als Teil eines 65 nm Prototypenchips produziert, auf dem er eine Fläche von 0.14 mm 2 belegt und eine maximale Taktfrequenz von 769 MHz erreicht.  ...  Dieser Ansatz wurde in ein abstraktes, hybrides Hardwaremodell formalisiert.  ...  65 nm process technology.  ... 
doi:10.11588/heidok.00015359 fatcat:2h3ekeqepnh3xlxkxxkpkbhfwi