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Recent Progress in the Development of Large-Capacity Integrated Silicon Photonics Transceivers

2019 IEICE transactions on electronics  
We report our recent progress in silicon photonics integrated device technology targeting on-chip-level large-capacity optical interconnect applications.  ...  To realize high-capacity data transmission, we successfully developed on-package-type silicon photonics integrated transceivers and demonstrated simultaneous 400 Gbps operation. 56 Gbps pulse-amplitude-modulation  ...  The author would like to express my profound gratitude to many colleagues of PE-TRA and Fujitsu Limited.  ... 
doi:10.1587/transele.2018odi0007 fatcat:z5ppfe4mefhglei27bkzo7znym

480 Gbps WDM Transmission Through an Al2O3:Er3+ Waveguide Amplifier

Themistoklis Chrysostomidis, Ioannis Roumpos, Konstantinos Fotiadis, Jinfeng Mu, Athanasios Manolis, Christos Vagionas, Meindert Dijkstra, Sonia M. Garcia Blanco, Theonitsa Alexoudi, Konstantinos Vyrsokinos
2021 Journal of Lightwave Technology  
Experimental results reveal bit-error rate values below the KR4-FEC limit of 2×10 -5 for all channels, without any DSP applied on the transmitter or receiver side for a 4×40 Gbps and40 Gbps data stream  ...  a static characterization and a dynamic evaluation for (a) 4×40 Gbps, (b) 8×40 Gbps and (c) 8×60 Gbps WDM transmissions achieving clearly open eye diagram in all cases.  ...  Fig. 10 Fig. 11 1011 Fig. 10 Back to back and normal BER measurements for the 8×40 Gbps transmission.  ... 
doi:10.1109/jlt.2021.3121467 fatcat:xcmtzx4z5bbyng3qzjjhwhpn24

CMOS smart pixel for free-space optical communication

Brian S. Leibowitz, Bernhard E. Boser, Kristofer S. J. Pister, Morley M. Blouke, John Canosa, Nitin Sampat
2001 Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications II  
A prototype of this receiver has been fabricated and demonstrated to receive a -32.6 dBm optical signal at 875 kbps with a bit error rate of 74 × 10 -6 .  ...  This paper discusses the theoretical performance of such receivers and the design of a single "smart pixel" for use in a 2.5 Mbps integrated CMOS imaging receiver.  ...  Examples of viable free-space optical communication links according to Eqs. 2.1 through 2.6. In all cases P trans = 5 mW, Äë = 10 nm, ë = 830 nm, R = 0.3 A/W, R BG = 0.3 W/W, T = 0.5 W/W.  ... 
doi:10.1117/12.426966 fatcat:x4uofidaufe5haaqa7karqmowq


2021 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  
in electronic circuits (e.g., in CMOS circuits).  ...  , Jan Craninckx; imec, Belgium Abstract: A low-power and high efficiency 135-155 GHz FMCW radar transmitter (TX) in 28 nm CMOS is presented.  ...  This workshop investigates digitally intensive transmit architectures and pre-distortion techniques that enhance the efficiency of transmitters and power amplifiers used in these next-generation wireless  ... 
doi:10.1109/rfic51843.2021.9490449 fatcat:wmoshjhq3nhxxljgu46qup325u

Spectrally and Power Efficient Optical Communication Systems [article]

Jose Krause Perin
2018 arXiv   pre-print
Increased traffic demands globally and in particular in short-reach links in data centers will require optical communication systems to continue scaling at an accelerated pace.  ...  For short-reach links in data centers, we propose low-power coherent receiver architectures that completely avoid high-speed analog-to-digital converters and digital signal processors.  ...  Moreover, a 40 Gb/s CDR in 90 nm CMOS consumes 48 mW [72] , excluding output buffers. high-speed ADCs and DSP [27] .  ... 
arXiv:1806.01945v1 fatcat:3wcwlgfqenaize5qwhhesjm2bm

Free-space transmission with passive 2D beam steering for multi-gigabit-per-second per-beam indoor optical wireless networks

Chin Wan Oh, Zizheng Cao, Eduward Tangdiongga, Ton Koonen
2016 Optics Express  
We experimentally characterized the beam-steered system and thoroughly evaluated the performance of steered channels using the spectrally efficient and robust discrete multitone modulation in a bandwidth-limited  ...  system deploying 10 GHz telecom transceivers.  ...  Acknowledgment This work is part of the Advanced Grant project Beam-steered Reconfigurable Optical-Wireless System for Energy-efficient communication (BROWSE), funded by the European Research Council within  ... 
doi:10.1364/oe.24.019211 pmid:27557201 fatcat:ujbqsjzinjgkvgwfsozysxenqy

3-D integrated heterogeneous intra-chip free-space optical interconnect

Berkehan Ciftcioglu, Rebecca Berman, Shang Wang, Jianyun Hu, Ioannis Savidis, Manish Jain, Duncan Moore, Michael Huang, Eby G. Friedman, Gary Wicks, Hui Wu
2012 Optics Express  
In this paper, we evaluate the performance of the proposed FSOI interconnect, and compare it to a waveguide-based optical interconnect with wavelength division multiplexing (WDM).  ...  Commercial 850-nm GaAs vertical-cavitysurface-emitting-lasers (VCSELs) and fabricated fused silica microlenses are 3-D integrated on top of the substrate.  ...  DE-FC52-08NA28302, the University of Rochester, and the New York State Energy Research and Development Authority.  ... 
doi:10.1364/oe.20.004331 pmid:22418191 fatcat:w6rgfl7qnjfjtmle5rtnkdnpmy

ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip

Sudeep Pasricha, Nikil Dutt
2008 2008 Asia and South Pacific Design Automation Conference  
In this paper we propose an optical ring bus (ORB) based on-chip communication architecture for next generation MPSoCs.  ...  We present experiments to show how ORB has the potential to provide superior performance (more than 2×) and significantly lower power consumption (a reduction of more than 10×) compared to traditionally  ...  113.6 90.2 74.7 TABLE III Power III Consumption of Optical Data Path (in mW) Tech Node 65 nm 45 nm 32 nm 22 nm Transmitter 18.4 8.6 6.0 5.0 Receiver 0.3 0.2 0.3 0.3 Total Optical Power 18.7 8.8 6.3  ... 
doi:10.1109/aspdac.2008.4484059 dblp:conf/aspdac/PasrichaD08 fatcat:x5cai7coc5dmjk7zrezhrgi2te

On-chip silicon photonic signaling and processing: a review

Jian Wang, Yun Long
2018 Science Bulletin  
In this paper, we review recent research progress in on-chip photonic signaling and processing on silicon photonics platforms.  ...  The advances in on-chip silicon photonic signaling and processing with favorable performance pave the way to integrate complete optical communication systems on a monolithic chip and integrate silicon  ...  $0.1 nm [180] width MZI MOS 10 Gbps 1.4 V 10 dB OOK $1550 nm, broadband [181] MRR pin 12.5 Gbps 3.5 V <0.5 dB OOK $1550 nm, $0.1 nm [182] width MZI Vertical 30 Gbps 6.5 V 7 dB OOK $1550 nm, broadband [  ... 
doi:10.1016/j.scib.2018.05.038 fatcat:v4al6zjlpzgv7jhmworyjjlfba

Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

Assaf Shacham, Keren Bergman, Luca P. Carloni
2008 IEEE transactions on computers  
Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs.  ...  The low loss properties of optical waveguides, combined with bit-rate transparency, allow for a photonic interconnection network that can deliver considerably higher bandwidth and lower latencies with  ...  For our case study, we assume a CMP implemented in a future 22 nm CMOS technology and hosting 36 processing cores, each requiring a peak bandwidth of 800 Gbps and an average bandwidth of 512 Gbps.  ... 
doi:10.1109/tc.2008.78 fatcat:pifja5v26vdwfmhxgfvtcpgxoa

The European BOOM Project: Silicon Photonics for High-Capacity Optical Packet Routers

L Stampoulidis, K Vyrsokinos, K Voigt, L Zimmermann, F Gomez-Agis, H J S Dorren, Zhen Sheng, D Van Thourhout, L Moerl, J Kreissl, B Sedighi, J C Scheytt (+2 others)
2010 IEEE Journal of Selected Topics in Quantum Electronics  
The BOOM "device portfolio" includes all-optical wavelength converters, ultradense wavedivision multiplexing (UDWDM) photodetectors, and high-speed transmitters; all based on silicon waveguide substrates  ...  Following this rationale, BOOM-as a European research initiative-aims to develop compact, cost-effective, and power-efficient silicon photonic components to enable optical Tb/s routers for current and  ...  Without optimization, the power to fully tune (5.3 nm) the double MZI structure on SOI was 600 mW.  ... 
doi:10.1109/jstqe.2009.2038238 fatcat:cmbrimrqf5h45aiqb7qvqs7gn4

An Energy-Efficient and Bandwidth-Scalable DWDM Heterogeneous Silicon Photonics Integration Platform

Di Liang, Sudharsanan Srinivasan, Geza Kurczveil, Bassem Tossoun, Stanley Cheung, Yuan Yuan, Antoine Descos, Yingtao Hu, Zhihong Huang, Peng Sun, Thomas Van Vaerenbergh, Chong Zhang (+5 others)
2022 IEEE Journal of Selected Topics in Quantum Electronics  
integrated circuit (PIC) applications.  ...  A 40-channel DWDM architecture and platform fabrication are discussed first, followed by experimental demonstration of each high-quality building block.  ...  5.1, 5.4, 5.3 and 6 dB [53] .  ... 
doi:10.1109/jstqe.2022.3181939 fatcat:p3hf2g4ztjbrlme4ssz5zy6vn4

Roadmap of optical communications

Erik Agrell, Magnus Karlsson, A R Chraplyvy, David J Richardson, Peter M Krummrich, Peter Winzer, Kim Roberts, Johannes Karl Fischer, Seb J Savory, Benjamin J Eggleton, Marco Secondini, Frank R Kschischang (+7 others)
2016 Journal of Optics  
Acknowledgments I thank Bob Tkach and Peter Winzer for valuable input and Jeff Hecht, whose 'A Fiber-Optic Chronology' provided the timeline of the early days of fiber communications.  ...  Acknowledgments We wish to sincerely thank all coauthors for their contributions and Jarlath McKenna at IOP Publishing for the coordination in putting this roadmap together.  ...  Example of transmitter and receiver functions combined into a single ASIC layout in 28 nm CMOS for metro optimized coherent applications. Figure 9 . 9 Figure 9.  ... 
doi:10.1088/2040-8978/18/6/063002 fatcat:vo3kd4v66vbwtjojvr4mmasn6u

2021 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 68

2021 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
-that appeared in this periodical during 2021, and items from previous years that were commented upon or corrected in 2021.  ...  Note that the item title is found only under the primary entry in the Author Index.  ...  ., +, TCSI March 2021 1160-1170 CMOS memory circuits A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS.  ... 
doi:10.1109/tcsi.2021.3134605 fatcat:txqhqj7nvnh6pp5dqloynq5jku

CMP network-on-chip overlaid with multi-band RF-interconnect

M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam
2008 High-Performance Computer Architecture  
We investigate the costs associated with this technology, and examine the latency and bandwidth benefits that it can provide.  ...  22% (max 24%) reduction in packet latency.  ...  Acknowledgments This research was supported in part by NSF grant CCF-0133997, Semiconductor Research Corporation grant 2005-TJ-1317, and DARPA grant SA5430-79952.  ... 
doi:10.1109/hpca.2008.4658639 dblp:conf/hpca/ChangCKNRST08 fatcat:tcpefvhkzzg7laduundhh3fyiy
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