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"Timing closure by design," a high frequency microprocessor design methodology

S. Posluszny, K. Lee, D. Meltzer, K. Nowka, J. Park, J. Peter, J. Silberman, O. Takahashi, P. Villarrubia, N. Aoki, D. Boerstler, P. Coulman (+5 others)
2000 Proceedings of the 37th conference on Design automation - DAC '00  
This paper presents a design methodology emphasizing early and quick timing closure for high frequency microprocessor designs.  ...  This methodology was used to design a Gigahertz class PowerPC microprocessor with 19 million transistors.  ...  This "Timing Closure by Design" methodology was instrumental in designing a 19 million transistor microprocessor and achieving its 1.0 Gigahertz frequency target with a small team on a tight schedule.  ... 
doi:10.1145/337292.337749 dblp:conf/dac/PoslusznyABCDFHKKLMNPPSTV00 fatcat:s7noxkmoyrhwpljfqll7pwqdka