Real-Time FPGA Implementation of Parallel Connected Component Labelling for a 4K Video Stream
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Marcin Kowalczyk,
Piotr Ciarach,
Dominika Przewłocka,
Hubert Szolc,
Tomasz Kryjak
Abstract
<jats:title>Abstract</jats:title>In this paper, a hardware implementation in reconfigurable logic of a single-pass connected component labelling (CCL) and connected component analysis (CCA) module is presented. The main novelty of the design is the support of a video stream in 2 and 4 pixel per clock format (2 and 4 ppc) and real-time processing of 4K/UHD video stream (3840 x 2160 pixels) at 60 frames per second. We discuss several approaches to the issue and present in detail the selected ones. The proposed module was verified in an exemplary application – skin colour areas segmentation – on the ZCU 102 and ZCU 104 evaluation boards equipped with Xilinx Zynq UltraScale+ MPSoC devices.
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