@misc{porret_hikavyy_granados_baudot_vohra_kunert_douhard_bogdanowicz_schaekers_kohen_et al._2018, 
  title={#AiMES2018_20181002_1400_Low-T-SiGe_Porret}, 
  DOI={10.1149/osf.io/3fvqn}, 
  abstractNote={<p>As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.</p>}, 
  publisher={The Electrochemical Society}, 
  author={Porret and Hikavyy and Granados and Baudot and Vohra and Kunert and Douhard and Bogdanowicz and Schaekers and Kohen and et al.}, 
  year={2018}, 
  month={Sep}
  }