Area Efficient Modified Array Multiplier

P Akshatha Shetty; Department of ECE R.V. College of Engineering Bengaluru ,India.; Dr. Kiran V; Department ECE R.V. College of Engineering Bengaluru, India.

doi:10.51201/jusst/21/09531

by P Akshatha Shetty, Department of ECE R.V. College of Engineering Bengaluru ,India., Dr. Kiran V, Department ECE R.V. College of Engineering Bengaluru, India.

Published in Journal of University of Shanghai for Science and Technology by ADD Technologies.

2021 Volume 23, Issue 09, p288-291

Abstract

Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.
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Date 2021-09-09

DOI 10.51201/jusst/21/09531

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