BibTeX
CSL-JSON
MLA
Harvard
8.4 LSI設計時の耐タンパ性検証手法(第8章:セキュリティ,<特集>ディペンダブルVLSIシステム)
8.4 Verification Method for Tamper Resistance in VLSI Design(8. Security,<Special Survey>Dependable VLSI System)
release_2ok567r2qjgrngmael47ancafm
by
Masaya YOSHIKAWA,
Daisuke SUZUKI,
Yohei HORI,
Takeshi FUJINO
Published
in The Journal of Reliability Association of Japan
by Reliability Engineering Association of Japan.
2013 Volume 35, Issue 8, p494
Archived Files and Locations
application/pdf
201.9 kB
file_zgrasdf5lbfbjcurvziv52qa6q
|
www.jstage.jst.go.jp (repository) web.archive.org (webarchive) |
Read Archived PDF
Preserved and Accessible
Work Entity
access all versions, variants, and formats of this works (eg, pre-prints)
access all versions, variants, and formats of this works (eg, pre-prints)
Cite This
Lookup Links
oaDOI/unpaywall (OA fulltext)
Crossref Metadata (via API)
Worldcat
SHERPA/RoMEO (journal policies)
wikidata.org
CORE.ac.uk
Semantic Scholar
Google Scholar
Crossref Metadata (via API)
Worldcat
SHERPA/RoMEO (journal policies)
wikidata.org
CORE.ac.uk
Semantic Scholar
Google Scholar