8.4 LSI設計時の耐タンパ性検証手法(第8章:セキュリティ,<特集>ディペンダブルVLSIシステム)
8.4 Verification Method for Tamper Resistance in VLSI Design(8. Security,<Special Survey>Dependable VLSI System) release_2ok567r2qjgrngmael47ancafm

by Masaya YOSHIKAWA, Daisuke SUZUKI, Yohei HORI, Takeshi FUJINO

Published in The Journal of Reliability Association of Japan by Reliability Engineering Association of Japan.

2013   Volume 35, Issue 8, p494

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