International Symposium on High-Performance Computer Architecture
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Showing first 25 out of 1,104 results
MemZip: Exploring unconventional benefits from memory compression
Ali Shafiee, Meysam Taassori, Rajeev Balasubramonian, Al Davis
2014
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2014.6835972 dblp:conf/hpca/ShafieeTBD14
A market approach for handling power emergencies in multi-tenant data center
Mohammad A. Islam, Xiaoqi Ren, Shaolei Ren, Adam Wierman, Xiaorui Wang
2016
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2016.7446084 dblp:conf/hpca/IslamRRWW16
Transportation-network-inspired network-on-chip
Hanjoon Kim, Gwangsun Kim, Seungryoul Maeng, Hwasoo Yeo, John Kim
2014
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2014.6835943 dblp:conf/hpca/KimKMYK14
Modeling cache performance beyond LRU
Nathan Beckmann, Daniel Sanchez
2016
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2016.7446067 dblp:conf/hpca/BeckmannS16
HRL: Efficient and flexible reconfigurable logic for near-data processing
Mingyu Gao, Christos Kozyrakis
2016
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2016.7446059 dblp:conf/hpca/GaoK16
Timing channel protection for a shared memory controller
Yao Wang, Andrew Ferraiuolo, G. Edward Suh
2014
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2014.6835934 dblp:conf/hpca/WangFS14
The runahead network-on-chip
Zimo Li, Joshua San Miguel, Natalie Enright Jerger
2016
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2016.7446076 dblp:conf/hpca/LiMJ16
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
Haakon Dybdahl, Per Stenstrom
2007
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2007.346180 dblp:conf/hpca/DybdahlS07
HARE: Hardware assisted reverse execution
Ioannis Doudalis, Milos Prvulovic
2010
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2010.5416651 dblp:conf/hpca/DoudalisP10
LiveSim: Going live with microarchitecture simulation
Sina Hassani, Gabriel Southern, Jose Renau
2016
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2016.7446098 dblp:conf/hpca/HassaniSR16
Dynamically detecting and tolerating IF-Condition Data Races
Shanxiang Qi, Abdullah A. Muzahid, Wonsun Ahn, Josep Torrellas
2014
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2014.6835923 dblp:conf/hpca/QiMAT14
TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture
Jaekyu Lee, Hyesoon Kim
2012
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2012.6168947 dblp:conf/hpca/LeeK12
Understanding GPU errors on large-scale HPC systems and the implications for system design and operation
Devesh Tiwari, Saurabh Gupta, James Rogers, Don Maxwell, Paolo Rech, Sudharshan Vazhkudai, Daniel Oliveira, Dave Londo, Nathan DeBardeleben, Philippe Navaux, Luigi Carro, Arthur Bland
2015
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2015.7056044 dblp:conf/hpca/TiwariGRMRVOLDN15
SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories
Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Moinuddin K. Qureshi
2018
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2018.00046 dblp:conf/hpca/SaileshwarNREQ18
Skinflint DRAM system: Minimizing DRAM chip writes for low power
Yebin Lee, Soontae Kim, Seokin Hong, Jongmin Lee
2013
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2013.6522304 dblp:conf/hpca/LeeKH013
Prediction router: Yet another low latency on-chip router architecture
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
2009
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2009.4798274 dblp:conf/hpca/MatsutaniKAY09
Dynamically Specialized Datapaths for energy efficient computing
Venkatraman Govindaraju, Chen-Han Ho, Karthikeyan Sankaralingam
2011
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2011.5749755 dblp:conf/hpca/GovindarajuHS11
Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules
Aditya Agrawal, Amin Ansari, Josep Torrellas
2014
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2014.6835978 dblp:conf/hpca/AgrawalAT14
Checkpointed early load retirement
N. Kirman, M. Kirman, M. Chaudhuri, J.F. Martinez
2005
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2005.9 dblp:conf/hpca/KirmanKCM05
Run-time monitoring with adjustable overhead using dataflow-guided filtering
Daniel Lo, Tao Chen, Mohamed Ismail, G. Edward Suh
2015
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2015.7056071 dblp:conf/hpca/LoCIS15
Adaptive Reliability Chipkill Correct (ARCC)
Xun Jian, R. Kumar
2013
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2013.6522325 dblp:conf/hpca/JianK13
An educational environment for teaching a course in computer architecture and organization
Jovan Djordjevic, Aleksandar Milenkovic, Nenad Grbanovic, Miroslav Bojovic
1998
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International Symposium on High-Performance Computer Architecture
doi:10.1145/1275176.1275180 dblp:conf/hpca/DjordjevicMGB98
Implications of high energy proportional servers on cluster-wide energy proportionality
Daniel Wong, Murali Annavaram
2014
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2014.6835925 dblp:conf/hpca/0001A14
Implications of Device Timing Variability on Full Chip Timing
Murali Annavaram, Ed Grochowski, Paul Reed
2007
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.2007.346183 dblp:conf/hpca/AnnavaramGR07
Sensitivity of parallel applications to large differences in bandwidth and latency in two-layer interconnects
A. Plaat, H.E. Bal, R.F.H. Hofman
1999
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International Symposium on High-Performance Computer Architecture
doi:10.1109/hpca.1999.744376 dblp:conf/hpca/PlaatBH99
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