International Conference on Parallel Architectures and Compilation Techniques
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Showing first 25 out of 1,073 results
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory
Adria Armejach, Azam Seyedi, Ruben Titos-Gil, Ibrahim Hur, Adri´n Cristal, Osman S. Unsal, Mateo Valero
2011
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1109/pact.2011.67 dblp:conf/IEEEpact/ArmejachSGHCUV11
Linearly compressed pages
Gennady Pekhimenko, Todd C. Mowry, Onur Mutlu
2012
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/2370816.2370911 dblp:conf/IEEEpact/PekhimenkoMM12
Leveraging on-chip networks for data cache migration in chip multiprocessors
Noel Eisley, Li-Shiuan Peh, Li Shang
2008
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/1454115.1454144 dblp:conf/IEEEpact/EisleyPS08
Adaptive reorder buffers for SMT processors
Joseph Sharkey, Deniz Balkan, Dmitry Ponomarev
2006
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/1152154.1152192 dblp:conf/IEEEpact/SharkeyBP06
SPARTAN
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
2006
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/1152154.1152194 dblp:conf/IEEEpact/BalkanSPG06
MapCG
Chuntao Hong, Dehao Chen, Wenguang Chen, Weimin Zheng, Haibo Lin
2010
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/1854273.1854303 dblp:conf/IEEEpact/HongCCZL10
Transparent runtime deadlock elimination
Hari K. Pyla, Srinidhi Varadarajan
2012
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/2370816.2370905 dblp:conf/IEEEpact/PylaV12
Feature selection and policy optimization for distributed instruction placement using reinforcement learning
Katherine E. Coons, Behnam Robatmili, Matthew E. Taylor, Bertrand A. Maher, Doug Burger, Kathryn S. McKinley
2008
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/1454115.1454122 dblp:conf/IEEEpact/CoonsRTMBM08
An empirical model for predicting cross-core performance interference on multicore processors
Josue Feliu, Julio Sahuquillo, Salvador Petit, Jose Duato
2013
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1109/pact.2013.6618810 dblp:conf/IEEEpact/FeliuSPD13
Compiling Dynamic Data Structures in Python to Enable the Use of Multi-core and Many-core Libraries
Bin Ren, Gagan Agrawal
2011
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1109/pact.2011.13 dblp:conf/IEEEpact/RenA11
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory
Carlos Villavieja, Vasileios Karakostas, Lluis Vilanova, Yoav Etsion, Alex Ramirez, Avi Mendelson, Nacho Navarro, Adrian Cristal, Osman S. Unsal
2011
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1109/pact.2011.65 dblp:conf/IEEEpact/VillaviejaKVERMNCU11
A low-cost memory remapping scheme for address bus protection
Lan Gao, Jun Yang, Marek Chrobak, Youtao Zhang, San Nguyen, Hsien-Hsin S. Lee
2006
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/1152154.1152169 dblp:conf/IEEEpact/GaoYCZNL06
Architecture Support for Improving Bulk Memory Copying and Initialization Performance
Xiaowei Jiang, Yan Solihin, Li Zhao, Ravishankar Iyer
2009
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1109/pact.2009.31 dblp:conf/IEEEpact/JiangSZI09
Making it practical and effective
Congming Chen, Wei Huo, Xiaobing Feng
2012
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/2370816.2370900 dblp:conf/IEEEpact/ChenH012
Approximating age-based arbitration in on-chip networks
Michael M. Lee, John Kim, Dennis Abts, Michael Marty, Jae W. Lee
2010
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/1854273.1854359 dblp:conf/IEEEpact/LeeKAML10
PS-Dir
Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, José Duato
2012
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/2370816.2370891 dblp:conf/IEEEpact/VallsRSGD12
Analytical Modeling of Pipeline Parallelism
Angeles Navarro, Rafael Asenjo, Siham Tabik, Calin Cascaval
2009
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1109/pact.2009.28 dblp:conf/IEEEpact/NavarroATC09
An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs
Calin Cascaval
2013
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1109/pact.2013.6618797 dblp:conf/IEEEpact/Cascaval13
Improving Run-Time Scheduling for General-Purpose Parallel Code
Alexandros Tzannes, Rajeev Barua, Uzi Vishkin
2011
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1109/pact.2011.49 dblp:conf/IEEEpact/TzannesBV11
Multi-mode energy management for multi-tier server clusters
Tibor Horvath, Kevin Skadron
2008
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/1454115.1454153 dblp:conf/IEEEpact/HorvathS08
Fairness-aware scheduling on single-ISA heterogeneous multi-cores
Tian Luo, Siyuan Ma, Rubao Lee, Xiaodong Zhang, Deng Liu, Li Zhou
2013
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1109/pact.2013.6618808 dblp:conf/IEEEpact/LuoML0LZ13
Layout-oblivious optimization for matrix computations
Huimin Cui, Qing Yi, Jingling Xue, Xiaobing Feng
2012
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/2370816.2370880 dblp:conf/IEEEpact/CuiYX012
Divergence Analysis and Optimizations
Bruno Coutinho, Diogo Sampaio, Fernando Magno Quintao Pereira, Wagner Meira Jr.
2011
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1109/pact.2011.63 dblp:conf/IEEEpact/CoutinhoSPM11
Mars
Bingsheng He, Wenbin Fang, Qiong Luo, Naga K. Govindaraju, Tuyong Wang
2008
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/1454115.1454152 dblp:conf/IEEEpact/HeFLGW08
Massively parallel skyline computation for processing-in-memory architectures
Vasileios Zois, Divya Gupta, Vassilis J. Tsotras, Walid A. Najjar, Jean-Francois Roy
2018
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International Conference on Parallel Architectures and Compilation Techniques
doi:10.1145/3243176.3243187 dblp:conf/IEEEpact/ZoisGTNR18
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