Asia and South Pacific Design Automation Conference
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Showing first 25 out of 3,373 results
Advanced tools for simulation and design of oscillators/PLLs
Xiaolue Lai, Jaijeet Roychowdhury
2007
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2007.358026 dblp:conf/aspdac/LaiR07
Rethinking error injection for effective resilience
Shahrzad Mirkhani, Hyungmin Cho, Subhasish Mitra, Jacob A. Abraham
2014
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2014.6742922 dblp:conf/aspdac/MirkhaniCMA14
Automating Logic Rectification by Approximate SPFDs
Yu-Shen Yang, Subarna Sinha, Andreas Veneris, Robert K. Brayton
2007
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2007.358019 dblp:conf/aspdac/YangSVB07
Buffering global interconnects in structured ASIC design
Tianpei Zhang, Sachin S. Sapatnekar
2005
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Asia and South Pacific Design Automation Conference
doi:10.1145/1120725.1120735 dblp:conf/aspdac/ZhangS05
BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies
Aadithya V. Karthik, Sayak Ray, Jaijeet Roychowdhury
2015
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2015.7059032 dblp:conf/aspdac/KarthikRR15
Thermal-driven multilevel routing for 3-D ICs
Jason Cong, Yan Zhang
2005
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Asia and South Pacific Design Automation Conference
doi:10.1145/1120725.1120787 dblp:conf/aspdac/CongZ05
Simultaneous redundant via insertion and line end extension for yield optimization
Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao
2011
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2011.5722266 dblp:conf/aspdac/LinLWKC11
MAIA
Luciano Ost, Aline Mello, José Palma, Fernando Moraes, Ney Calazans
2005
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Asia and South Pacific Design Automation Conference
doi:10.1145/1120725.1120741 dblp:conf/aspdac/OstMPMC05
An efficient solution to the storage correspondence problem for large sequential circuits
Wanlin Cao, Duncan M. H. Walker, Rajarshi Mukherjee
2001
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Asia and South Pacific Design Automation Conference
doi:10.1145/370155.370318 dblp:conf/aspdac/CaoWM01
Control-Flow Aware Communication and Conflict Analysis of Parallel Processes
Axel Siebenborn, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel
2007
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2007.357788 dblp:conf/aspdac/SiebenbornVBR07
Statistical analysis of process variation based on indirect measurements for electronic system design
Ivan Ukhov, Mattias Villani, Petru Eles, Zebo Peng
2014
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2014.6742930 dblp:conf/aspdac/UkhovVEP14
A digital audio signal processor for cellular phone application
Jeongsik Yang, Chanhong Park, Beomsup Kim
1995
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Asia and South Pacific Design Automation Conference
doi:10.1145/224818.224896 dblp:conf/aspdac/YangPK95
Reducing Dynamic Dispatch Overhead (DDO) of SLDL-synthesized embedded software
Jiaxing Zhang, Sanyuan Tang, Gunar Schirner
2015
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2015.7059080 dblp:conf/aspdac/ZhangTS15
Multi-level placement for large-scale mixed-size IC designs
Chin-Chih Chang, Jason Cong, Xin Yuan
2003
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Asia and South Pacific Design Automation Conference
doi:10.1145/1119772.1119835 dblp:conf/aspdac/ChangCY03
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs
M. S. Haque, A. Kumar, Yajun Ha, Qiang Wu, Shaobo Luo
2013
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2013.6509615 dblp:conf/aspdac/HaqueKHWL13
Co-synthesis with custom ASICs
Yuan Xie, Wayne Wolf
2000
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Asia and South Pacific Design Automation Conference
doi:10.1145/368434.368591 dblp:conf/aspdac/XieW00
Block based statistical timing analysis with extended canonical timing model
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
2005
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Asia and South Pacific Design Automation Conference
doi:10.1145/1120725.1120816 dblp:conf/aspdac/ZhangHC05a
A 128-way FPGA platform for the acceleration of KLMS algorithm
Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren
2015
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2015.7058925 dblp:conf/aspdac/RenYCZR15
A reconfigurable accelerator for neuromorphic object recognition
Jagdish Sabarad, Srinidhi Kestur, Mi Sun Park, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla
2012
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2012.6165067 dblp:conf/aspdac/SabaradKPDNCK12
Throughput optimization for latency-insensitive system with minimal queue insertion
Juinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho
2011
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2011.5722257 dblp:conf/aspdac/HuangCH11
Sparse statistical model inference for analog circuits under process variations
Yan Zhang, Sriram Sankaranarayanan, Fabio Somenzi
2014
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2014.6742932 dblp:conf/aspdac/ZhangSS14
Security analysis of Anti-SAT
Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
2017
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2017.7858346 dblp:conf/aspdac/YasinMSR17
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs
Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong
2011
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2011.5722195 dblp:conf/aspdac/WangMDWHC11
Methodology for high level estimation of FPGA power consumption
Vijay Degalahal, Tim Tuan
2005
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Asia and South Pacific Design Automation Conference
doi:10.1145/1120725.1120986 dblp:conf/aspdac/DegalahalT05
Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems
Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amirali Ghofrani, Shiyuan Yang, Kwang-Ting Tim Cheng
2012
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Asia and South Pacific Design Automation Conference
doi:10.1109/aspdac.2012.6165030 dblp:conf/aspdac/ZhengLSGYC12
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